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A conventional technique in which an alignment mark is formed on a semiconductor wafer for alignment and the alignment mark is detected by using an image processing technique is disclosed in Japanese Patent Application Laid-Open No. 2001-93985 (Patent Document 1). In this technique, it is necessary to properly set a light source position for exposure in order to improve the alignment accuracy. For this purpose, the light source position is adjusted while detecting the alignment mark by using the image processing technique, in which a margin for adjustment is assured. That is, the light source position is shifted while taking into consideration the margin for the adjustment. This margin for the adjustment is not a margin for a displacement itself of the alignment mark.
However, when an alignment error occurs, the margin for the adjustment is reduced in the technique described in Patent Document 1. This may reduce the alignment accuracy and lower the accuracy for alignment of fine patterns on a semiconductor wafer. In addition, the margin for the alignment may be set smaller to improve the alignment accuracy
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